This invention relates to wafer handling, and more particularly, to an apparatus and a method for handling wafers in a fabrication processing sequence.
In a number of applications of commercial importance, thin fragile disk-like elements must be picked up, transported and mounted for processing. These elements comprise, for example, semiconductor wafers. Such wafers must be handled carefully to avoid contamination, scratching, chipping or breaking. During and between processing steps, the handling of such fragile wafers in a high-throughput manner that meets stringent cleanliness requirements poses a considerable practical challenge.
One illustrative system designed for processing wafers is described in U.S. Pat. No. 4,298,443. The described system is designed to carry out dry etching of wafers. In that system, wafers to be etched are loaded into tray members. The wafer-carrying tray members are then mounted in the reaction chamber of the etching system on the respective facets of a longitudinally extending multifaceted electrode.
After the wafers have been etched in the system described in the aforecited patent, the tray members are removed from the chamber. The wafers are subsequently unloaded from the members and moved to a storage medium to await the next step in the wafer processing sequence.
Thus, in the course of the specified wafer etching process, wafers must be picked up and transported a number of times. They must be moved into and out of the storage medium. Further, they must also be loaded into and out of the wafer-carrying tray members. These various operations as well as other steps in the overall wafer fabrication sequence impose a number of difficult requirements on the design of a wafer handling system. A critical part of such a system comprises a suitable wafer pickup tool.
Accordingly, considerable effort has been expended by workers directed at developing improved wafer handling techniques. It was recognized that such efforts, if successful, could lead to wafer handling apparatus and methods for significantly enhancing the efficiency and thereby lowering the cost of wafer fabrication. In turn, the cost of commercially important devices such as integrated circuits formed on the wafers could thereby be reduced.